1. Field of the Invention
This invention relates to semiconductor devices and in particular to integarted circuit structures.
2. Prior Art
Numerous techniques for electrically isolating semiconductor structures have been developed and are well-known in the art of semiconductor fabrication. See, for a list of papers describing such techniques, A. H. Agajanian's article entitled "A Biography on Semiconductor Device Isolation Techniques," Solid State Technology, April, 1975. Also well-known are methods of forming oxidized isolation regions in integrated circuit structures. For example, U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure" issued Mar. 7, 1972, to Douglas L. Peltzer (hereinafter referred to as the Peltzer patent) discloses techniques for fabricating substantially smaller transistors, diodes, and resistors than the then existing prior art. In one such technique disclosed by the Peltzer patent, an epitaxial layer of silicon is formed on a silicon substrate and divided into electrically isolated pockets by a grid of oxidized regions of the silicon material in conjunction with a laterally extending PN isolation junction. Active and/or passive components such as diodes, transistors, and resistors may be formed in the electrically isolated pockets.
In the fabrication of vertical transistors according to the Peltzer patent and using a P type substrate and a P type epitaxial layer, a buried layer of N conductivity type semiconductor material (typically called a "buried collector region," "buried collector layer," or a "buried collector") formed in selected locations of the substrate and the epitaxial silicon layer may serve as a collector. In one embodiment, one or more emitters may then be formed in selected regions by diffusion or by otherwise introducing suitable N type impurities into the upper surface of the epitaxial silicon. The epitaxial silicon material beneath each emitter, but above the collector, functions as the base of the transistor. Ohmic contact to the buried collector regions may be achieved by diffusing, or otherwise inserting, a selected N type impurity into selected regions of the epitaxial silicon to convert these regions to the same conductivity type as the buried collector if the epitaxial layer is not already of the same conductivity type as the buried collector.
One problem arising in the manufacture of integrated circuits which utilize various embodiments of the oxide isolation techniques disclosed in the Peltzer patent and elsewhere is channel inversion or MOS channeling. Channel inversion may occur in oxide isolated integrated circuit structures between adjacent but noncontiguous N type buried collector regions. Usually occurring at the interface between the P type silicon and the overlying oxide, channel inversion results from a variety of causes, for example, from the presence of impurities in the oxide, typically sodium ions having a net positive charge which "mirror", or attract, electrons in the underlying P type silicon. If enough electrons are attracted, a very thin region of the P type silicon will be converted to N type semiconductor material, creating an N type channel between the adjacent buried collector regions. Channel inversion causes theoretically isolated collector regions to be effectively electrically connected to each other, thereby degrading or thwarting the function of the device and/or circuit. Channel inversion usually cannot be completely prevented by forming oxide of high purity, as only a few parts per billion of sodium impurity in the oxide may be sufficient to cause channel inversion in a lightly doped substrate.
Channel inversion has been frequently studied in conjunction with the manufacture of MOS transistors in which it is necessary to prevent unwanted leakage currents and to control threshold voltages. Three of the standard MOS techniques for preventing channel inversion are: (1) channel stops (which are heavily doped regions adjacent selected surfaces), (2) other forms of surface doping control, and (3) phosphorus gettering of sodium impurities in surface oxides.
One technique for preventing channel inversion is the formation of a guard ring surrounding selected regions of the integrated circuit structure. The guard ring is usually created by diffusing, or otherwise inserting, a selected impurity into desired locations of the semiconductor material thereby to create inversion-preventing regions of selected conductivity type and impurity concentration.
A further technique for preventing channel inversion has been employed by B. T. Murphy at Bell Laboratories, and is discussed in W. J. Evans et al, "Oxide Isolated Monolithic Technology and Applications," IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 5, October 1973. This reference discloses that after completely forming the oxide isolation for a given device, gallium is diffused through the oxide to strongly dope those regions of semiconductor material beneath the oxide, thereby preventing channel inversion by creating regions of opposite conductivity type to the buried collector regions.
U.S. Pat. No. 3,873,383 issued Mar. 25, 1975, on an application of Kooi and entitled "Integrated Circuits with Oxidation-Junction Isolation and Channel Stop" discloses a channel stop formed in an oxide-insolated integrated circuit structure. While Kooi discloses using a predeposition region to contact the substrate beneath the epitaxial layer in the absence of a buried collector region, Kooi fails to suggest or disclose the potential advantageous use of the channel stop region to provide a conductive buried region which conducts current in a lateral direction, and thereby makes possible a significant reduction in memory cell size.